Circuit to test loaded inverter propagation delay
*
* Run for 10ns with an initial timestep of 50ps
.tran 50p 10n
*
* Vdd voltage
vdd vdd 0 5.0
* Input squarewave
vin in 0 0.0 pulse(0.0 5.0 0.0 50p 50p 2.5n 5n)
* The inverter being checked
x1 vdd in out inv
* Four inverters hooked to it's output
x2 vdd out out1 inv
x3 vdd out out2 inv
x4 vdd out out3 inv
x5 vdd out out4 inv
* The definition of the inverter
.subckt inv vdd in out
m1 out in vdd vdd pfet l=1.2u w=72.2u
m2 out in 0 0 nfet l=1.2u w=24.4u
.ends inv
* Include spice models
.include fets.spi
* The end of the spice input file
.end